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 M62352P/FP/GP
8-bit 12ch D/A Converter with Buffer Amplifiers
REJ03D0868-0300 Rev.3.00 Mar 25, 2008
Description
The M62352 is an integrated circuit semiconductor of CMOS structure with 12 channels of built-in D/A converters with output buffer operational amplifiers. The 3-wire serial interface method is used for the transfer format of digital data to allow connection with microcomputer with minimum wiring. It is able to cascading serial use with DO terminal. The output buffer operational amplifier operates in the whole voltage range from power supply to ground for both input/output.
Features
* 12-bit serial data input (3-wire serial data transfer method) * Highly stable output buffer operational amplifier allow operation in the all voltage range from power supply to ground.
Application
Adjustment/control of industrial or home-use electronic equipment, such as VTR camera, VTR set, TV, and CRT display.
Block Diagram
GND 20 AO2 19 AO1 18 DI 17 CLK 16 LD 15 DO 14 AO12 13 AO11 12 VCC 11
12-bit shift register
D0 1 2 3 4 5 6 D7 D8 9 10 D11
8-bit R-2R + segment D/A converter
+ -
Ch2 8-bit latch 1
+ -
D/A
Address decoder
........ (12)
12
D/A
11
+ -
+ -
D/A
L
(8)
L
L
(12)
.... (12)
8-bit latch Ch3
8-bit R-2R + segment D/A converter
L
4 5
L
6
L
7
L
8
L
9
L
10
L
D/A
D/A
D/A
D/A
D/A
D/A
D/A
+ -
+ -
+ -
+ -
+ -
+ -
+ -
+ -
Buffer OP AMP
1 VSS (VrefL)
2 AO3
3 AO4
4 AO5
5 AO6
6 AO7
7 AO8
8 AO9
9 AO10
10 VDD (VrefU)
REJ03D0868-0300 Rev.3.00 Mar 25, 2008 Page 1 of 9
M62352P/FP/GP
Pin Arrangement
M62352P/FP/GP
VSS (VrefL) AO3 AO4 AO5 AO6 AO7 AO8 AO9 AO10 VDD (VrefU) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 GND AO2 AO1 DI CLK LD DO AO12 AO11 VCC
(Top view) Outline: PRDP0020BA-A (20P4B) PRSP0020DA-A (20P2N-A) 20P2E-A
Pin Description
Pin No. 17 14 16 15 18 19 2 3 4 5 6 7 8 9 12 13 11 20 10 1 Pin Name DI DO CLK LD AO1 AO2 AO3 AO4 AO5 AO6 AO7 AO8 AO9 AO10 AO11 AO12 VCC GND VDD VSS Function Serial data input terminal Serial data output terminal Serial clock input terminal LD terminal input high level then latch circuit data load 8-bit D/A converter output terminal
Power supply terminal Digital and analog common GND D/A converter upper reference voltage input terminal D/A converter lower reference voltage input terminal
REJ03D0868-0300 Rev.3.00 Mar 25, 2008 Page 2 of 9
M62352P/FP/GP
Block Diagram for Explanation of Terminals
VCC
11
GND
20
DI CLK
17 16
D0 D1 D2 D3
12-bit shift register
D4 D5 D6 D7 D8 D9 D10 D11
14
DO
(8) (12)
Address decoder
1 2 3 4 5 6 7 8 9 10 11 12
15
LD
D0
.....
D7
D0
.....
D7
8-bit latch 8-bit R-2R D/A
............................... 12 ...............................
8-bit latch 8-bit R-2R D/A
+ -
18
+ -
.........................................
10
13
1
AO1 VDD (VrefU)
AO12
VSS (VrefL)
Absolute Maximum Ratings
Item Supply voltage D/A converter upper reference voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Symbol VCC VDD VIN VO Pd Topr Tstg Ratings -0.3 to +7.0 -0.3 to +7.0 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 350 (P) / 300 (FP) / 150 (GP) -20 to +85 -40 to +125 Unit V V V V mW C C
REJ03D0868-0300 Rev.3.00 Mar 25, 2008 Page 3 of 9
M62352P/FP/GP
Electrical Characteristics
Digital Part (VCC, VrefU = +5 V 10%, VCC VrefU, GND, VrefL = 0 V, Ta = -20C to +85C, unless otherwise noted)
Item Supply voltage Circuit current Input leak current Input low voltage Input high voltage Output low voltage Output high voltage Symbol VCC ICC IILK VIL VIH VOL VOH Min 4.5 -- -10 -- 0.8 VCC -- VCC - 0.4 Limits Typ 5.0 1.6 -- -- -- -- -- Max 5.5 3.2 10 0.2 VCC -- 0.4 -- Unit V mA A V V V V Test Conditions CLK = 1 MHz operation IOA = 0 A VIN = 0 to VCC
IOL = 2.5 mA IOH = -400 A
Analog Part (VCC, VrefU = +5 V 10%, VCC VrefU, Ta = -20C to +85C, unless otherwise noted)
Item Current dissipation D/A converter upper reference voltage range D/A converter lower reference voltage range Buffer amplifier output voltage range Buffer amplifier output drive range Differential nonlinearity error Nonlinearity error Zero code error Full scale error Output capacitive load Buffer amplifier output impedance Symbol IDD VDD VSS Min -- 3.5 GND Limits Typ 1.5 -- -- Max 3.5 VCC VCC - 3.5 Unit mA V V Test Conditions VrefU = 5 V, VrefL = 0 V, IAO = 0 A Data condition; at maximum current The output dose not necessarily be the value within the reference voltage setting range. The output value is determined by the buffer amplifier output voltage range (VAO) IOA = 100 A IOA = 500 A Upper side saturation voltage = 0.3 V Lower side saturation voltage = 0.2 V VrefU = 4.79 V VrefL = 0.95 V VCC = 5.5 V (15 mV/LSB) Without load (IOA = 0 A)
VAO IAO SDL SL SZERO SFULL CO RO
0.1 0.2 -1 -1.0 -1.5 -2 -2 -- --
-- -- -- -- -- -- -- -- 5
VCC - 0.1 VCC - 0.2 1 1.0 1.5 2 2 0.1 --
V mA LSB LSB LSB LSB F
REJ03D0868-0300 Rev.3.00 Mar 25, 2008 Page 4 of 9
M62352P/FP/GP
AC Characteristics
(VCC, VrefU = +5 V 10%, VCC VrefU, GND, VrefL = 0 V, Ta = -20 to +85C, unless otherwise noted)
Item Clock "L" pulse width Clock "H" pulse width Clock rise time Clock fall time Data setup time Data hold time LD setup time LD hold time LD "H" pulse width Data output delay time D/A output setting time Symbol tCKL tCKH tCR tCF tDCH tCHD tCHL tLDC tLDH tDO tLDD Min 200 200 -- -- 30 60 200 100 100 70 -- Limits Typ -- -- -- -- -- -- -- -- -- -- -- Max -- -- 200 200 -- -- -- -- -- 350 300 Unit ns ns ns ns ns ns ns ns ns ns s Test Conditions
CL 100 pF CL 100 pF VAO: 0.5 4.5 V The time until the output becomes the final value of 1/2 LSB
Timing Chart
tCR tCKH tCF
CLK
tCKL
DI
tLDH tDCH tCHD tCHL
tLDC
LD
tLDD
D/A output
tDO
DO output
REJ03D0868-0300 Rev.3.00 Mar 25, 2008 Page 5 of 9
M62352P/FP/GP
Digital Data Format
Last LSB D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 First MSB D11
DAC data
DAC select data
DAC Data
D0 0 1 0 1 : 0 1 Note: D1 0 0 1 1 : 1 1 D2 0 0 0 0 : 1 1 D3 0 0 0 0 : 1 1 D4 0 0 0 0 : 1 1 D5 0 0 0 0 : 1 1 D6 0 0 0 0 : 1 1 D7 0 0 0 0 : 1 1 D/A Output (VrefU - VrefL) / 256 x 1 + VrefL (VrefU - VrefL) / 256 x 2 + VrefL (VrefU - VrefL) / 256 x 3 + VrefL (VrefU - VrefL) / 256 x 4 + VrefL : (VrefU - VrefL) / 256 x 255 + VrefL VrefU
VrefU = VDD, VrefL = VSS
DAC Select Data
D8 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D9 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D10 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D11 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DAC Selection Don't care AO1 select AO2 select AO3 select AO4 select AO5 select AO6 select AO7 select AO8 select AO9 select AO10 select AO11 select AO12 select Don't care Don't care Don't care
Timing Chart (Model)
MSB DI D11 D10 D9 D8
.............
LSB D2 D1 D0
CLK
..................
LD
D/A output
REJ03D0868-0300 Rev.3.00 Mar 25, 2008 Page 6 of 9
M62352P/FP/GP
Typical Characteristics
Upper Side Saturation Voltage vs. Output Source Current
150 150
Lower Side Saturation Voltage vs. Output Sink Current
Upper Side Saturation Voltage VCC-VAOSATU (mV)
Lower Side Saturation Voltage VAOSATL (mV)
0 200 400 600 800 1000
100
100
50
50
0
0 0 200 400 600 800 1000
Output Source Current IAOD (A)
Output Sink Current IAOS (A)
REJ03D0868-0300 Rev.3.00 Mar 25, 2008 Page 7 of 9
M62352P/FP/GP
Package Dimensions
JEITA Package Code P-SDIP20-6.3x19-1.78 RENESAS Code PRDP0020BA-A Previous Code 20P4B MASS[Typ.] 1.0g
20
11
1
10
c
*1
e1
E
*2 D
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
A
A2
Reference Dimension in Millimeters Symbol
e SEATING PLANE
*3 b 3
bp
e1 D E A A1 A2 bp b3 c e L
Min Nom Max 7.32 7.62 7.92 18.8 19.0 19.2 6.15 6.3 6.45 4.5 0.51 3.3 0.38 0.48 0.58 0.9 1.0 1.3 0.22 0.27 0.34 0 15 1.528 1.778 2.028 3.0
JEITA Package Code P-SOP20-5.3x12.6-1.27
L
RENESAS Code PRSP0020DA-A
Previous Code 20P2N-A
MASS[Typ.] 0.3g
20 11
HE
*1
E
A1
F
1 Index mark
10
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
c
*2 D
A2
A1
Reference Symbol
Dimension in Millimeters
*3 e bp y Detail F
D E A2 A1 A bp c HE e y L
Min Nom Max 12.5 12.6 12.7 5.2 5.3 5.4 1.8 0.1 0.2 0 2.1 0.35 0.4 0.5 0.18 0.2 0.25 0 8 7.5 7.8 8.1 1.12 1.27 1.42 0.1 0.4 0.6 0.8
A
REJ03D0868-0300 Rev.3.00 Mar 25, 2008 Page 8 of 9
L
M62352P/FP/GP
20P2E-A
EIAJ Package Code SSOP20-P-225-0.65 JEDEC Code -- Weight(g) 0.08 Lead Material Alloy 42
Plastic 20pin 225mil SSOP
e b2
20
11
HE
E
F Recommended Mount Pad Symbol
1 10
e1
A
G
D
b
e
x
M
A2
A1
y
c z Z1 Detail G Detail F
A A1 A2 b c D E e HE L L1 z Z1 x y b2 e1 I2
Dimension in Millimeters Min Nom Max -- -- 1.45 0 0.1 0.2 -- -- 1.15 0.17 0.32 0.22 0.13 0.15 0.2 6.4 6.5 6.6 4.3 4.4 4.5 -- -- 0.65 6.2 6.4 6.6 0.3 0.5 0.7 -- -- 1.0 0.325 -- -- 0.475 -- -- 0.13 -- -- -- -- 0.1 0 -- 10 0.35 -- -- 5.8 -- -- -- -- 1.0
L1
REJ03D0868-0300 Rev.3.00 Mar 25, 2008 Page 9 of 9
L
I2
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. 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Colophon .7.2


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